Cpu scheduling methods based on relative time quantum for dual core environments

ABSTRACT

The present disclosure is directed to dual core processor scheduling based on relative time quantum. A time quantum is calculated by taking the average of the process burst times for each roughly half portion of a ready queue list and then applying addition and subtraction to the relative values. A first CPU is assigned the quantum based on addition while the second CPU is assigned the quantum based on subtraction.

STATEMENT OF PRIOR DISCLOSURE

Aspects of this technology are described in an article “Design andEvaluation of CPU Scheduling Algorithms Based on Relative Time Quantum:Variations of Round Robin Algorithm” published in Journal ofComputational and Theoretical Nanoscience, Vol. 15, No. 8, pp.2483-2488, on Aug. 1, 2018, which is incorporated herein by reference inits entirety.

BACKGROUND Technical Field

The present disclosure is directed to dual core processor schedulingbased on a relative time quantum. In one aspect the time quantum iscalculated by taking the average of the process burst times for eachhalf of a ready queue list and then applying addition and subtraction tothe relative values. A first CPU is assigned the quantum based onaddition while the second CPU is assigned the quantum based onsubtraction.

Description of Related Art

The “background” description provided herein is for the purpose ofgenerally presenting the context of the disclosure. Work of thepresently named inventors, to the extent it is described in thisbackground section, as well as aspects of the description which may nototherwise qualify as prior art at the time of filing, are neitherexpressly or impliedly admitted as prior art against the presentinvention.

In the field of computing resources, resource optimization is an areawhich needs constant improvement. With the advent of cloud computingenvironments and big data applications, improved computing resourceusage is required. The traditional approaches of process scheduling needto be further improved.

An operating system is a program that manages the hardware part of thecomputer. It is an intermediary program between the user and thecomputer. Processing unit (PU) scheduling is of high interest inmultiprogramming operating systems, as by switching the CPU betweendifferent processes (also called content switching), the performance andefficiency of a computer can be enhanced. This field has further gainedimportance due to the emergence of architectural frameworks such ascloud computing, service oriented architectures, mobile computing etc.(See A. Silberschatz, P. B. Galvin, and G. Gagne, “CPU Scheduling,Operating System Concepts”, 9th Ed., Wiley Publishers (2012), p. 972; Y.Li, M. Chen, W. Dai, and M. Qiu, IEEE Systems Journal 11, 96 (2017); A.Tchernykh, “Scheduling algorithms for distributed cosmic ray detectionusing Apache Mesos”, High Performance Computing: Third Latin AmericanConference, CARLA 2016, Mexico City, Mexico, August-September, April,Springer, 2016, Revised Selected Papers (2017), Vol. 697, p. 359; R.Tyagi and S. K. Gupta, “A survey on scheduling algorithms for paralleland distributed systems”, Silicon Photonics and High PerformanceComputing, Springer, Singapore (2018), pp. 51-64; H. G. Tani and C. ElAmrani, Journal of Data Mining and Digital Humanities, Special Issue onScientific and Technological Strategic Intelligence (2016); P. Thakurand M. Mahajan, International Journal of Modern Computer Science 5(2017); and M. A. Rodriguez and R. Buyya, “Concurrency and Computation:Practice and Experience 29” (2017), each incorporated herein byreference in their entirety).

CPU scheduling involves complex mechanisms which assign CPUs to multipleprocesses directed to a CPU. Some traditional CPU scheduling algorithmsare now described.

A processor-based CPU scheduling (TPBCS) algorithm, in which oneprocessor is exclusively assigned to CPU-intensive processes and theother processor is exclusively assigned to I/O-intensive processes hasbeen used in the past. This approach dispatches the processes to theappropriate processor according to their percentage of CPU or I/Orequirement. After the processes are dispatched to respectiveprocessors, the time quantum is calculated randomly, and the processesare executed in an increasing order of their burst time. (See H. S.Behera, Jajnaseni Panda, Dipanwita Thakur and Subasini Saho, “A NewProposed Two Processor Based CPU Scheduling Algorithm with Varying Timequantum for Real Time Systems”, incorporated herein by reference in itsentirety).

First-Come-First-Serve (FCFS) is a CPU scheduling algorithm whichassigns a CPU to the process which comes first in the ready queue. Thisalgorithm is non-preemptive in nature and is considered as the simplesttechnique applied. FCFS is a widely used scheduling methodology, butalso has shortcomings. If a process is too long, the process has to waitat the end of the queue, and not get time in the CPU. (See Md. MamunurRashid and Md. Nasim Adhtar, Journals of Applied Sciences 6, 2036(2009), incorporated herein by reference in its entirety).

Another known algorithm is priority based scheduling, which works byassigning priorities to each process. Each process in a ready queue isassigned priority based on certain criteria. Highest priorityjobs/processes are given to the CPU first, following the processes withlow priority. Some of the processes arrive with equivalent priority;their scheduling is decided by a first come first serve methodology.(See I. Singh Rajput and D. Gupta, J. Adv. Eng. Technol. 2, 120 (2013),incorporated herein by reference in its entirety).

Another widely used algorithm is known as shortest job first. Thisalgorithm works by selecting the process which has shortest timerequirement for the CPU. The advantage of this approach is that itsturnaround time is less for most processes, but starvation may occur.(See S. Shukla and L. Kishore, International Journal of Engineering,Management and Sciences (IJEMS) 1 (2014), incorporated herein byreference in its entirety).

The most widely used scheduling algorithm is Round Robin. This algorithmuses FCFS and is preemptive. A small time quantum is assigned to eachprocess and then a time slice is taken for each process. As the timequantum for a particular process expires, the CPU is forcefully assignedto the next process in the ready queue, thus using context switching.The turnaround time of this process depends upon the size of the timequantum assigned. This algorithm also offers some shortcomings in termsof its average waiting time, which may be high due to the application ofcontext switching and FCFS. (See Qudsia Mateen, Ujala Niazi, Marwah, andSobia Khalid, International Journal of Computer and Communication SystemEngineering (IJCCSE) 2, 139 (2015), incorporated herein by reference inits entirety).

Another CPU scheduling technique is known as multilevel queuescheduling. Multilevel queue scheduling divides the workload of theprocesses into different queues. This algorithm differs from othertechniques by using different scheduling algorithms on each of thequeues. A process in the ready queue is assigned priority based on itsstatus, whether it is a foreground process or a background process.Foreground processes are given high priority while background processesare assigned as low priority. High priority processes are placed in theupper queues. These queues are given priority over queues havingbackground processes. Process(es) jump from one queue to another basedon its assigned scheduling algorithm.

Another similar technique which works on the mechanism of multilevelqueue scheduling is multilevel feedback queue scheduling. A similarprocess is followed, but in this technique the scheduler keeps analyzingthe behavior of the process and, based on the behavior, the algorithmchanges the priority of the processes, going from high to lower levelpriority processes.

A variation of round robin algorithm has been proposed, in which theround robin algorithm changes the time quantum to a dynamic timequantum. (See M. V. Ahamad, International Journal of Advanced Researchin Computer Science 8 (2010), incorporated herein by reference in itsentirety). In a previous work by the instant inventors, a variation ofround robin was presented in which the time quantum assigned to eachprocess was the average of the two middle processes. (See Saeeda Bibi,Farooque Azam, Sameera Amjad, Wasi Haider Butt, Hina Gull, Rashid Ahmed,and Yasir Chaudhry, “An Efficient SJRR CPU Scheduling Algorithm”,International Journal of Computer Science and Information Security 8(2)(2010),https://www.scribd.com/document/32950807/An-Efficient-SJRR-CPU-Scheduling-Algorithm,incorporated herein by reference in its entirety).

In an aspect of the present disclosure, the two CPUs of a dual coreprocessor each perform mixed jobs, none of which is exclusivelydedicated to either I/O is CPU intensive. [Diane is something missingfrom the text here?] All jobs/processes are divided between the CPUsbased on their sequence in the processor queue. The difference betweenthe present disclosure and previous scheduling techniques is in thecalculation of the time quantum.

In the present disclosure, the time quantum is calculated by taking theaverage of the process burst time for each half of a ready queue listand then applying addition and subtraction to the relative values. OneCPU is directed to use a scheduling technique having a quantum based onthe added values while other is directed to use a scheduling techniquehaving a quantum based on the subtracted values. Thus, a dual coreperforms both tasks simultaneously based on different schedulingtechniques. Both scheduling techniques have been simulated and givenrandom burst time. Simulation results have been compared with the roundrobin scheduling method. The simulation results demonstrate thatscheduling performance is significantly improved as compared to that oftraditional round robin scheduling.

SUMMARY

In an exemplary embodiment, a scheduling method for use in processscheduling in a dual core computer is disclosed. The method includesdividing a ready queue of P processes into a first list of n processesand a second list of m processes, where n+m equals P, averaging theburst times of the processes in each list, adding the averages togenerate a first quantum and subtracting the averages to generate asecond quantum, assigning the first quantum to a first CPU of the dualcore computer; and assigning the second quantum to a second CPU of thedual core computer.

In another exemplary embodiment, a scheduling system for use in a dualcore computer is disclosed. The system includes an input/output devicewhich receives process requests and outputs processing results, a readyqueue which receives processes P from the I/O device, each processhaving a predetermined burst time, B, a scheduler which has circuitryconfigured to divide the ready queue into a first list of n processesand a second list of m processes, where n+m equals P, an averager whichaverages burst times of the processes in each list, a summer which addsthe averages to generate a first quantum, a subtraction module whichdetermines the absolute value of the difference between the averagevalues and generates a second quantum, and an assignment module forassigning a process P_(i)(n) from the first list to a first CPU and aprocess P_(j)(m) from the second list to a second CPU₂, where i=1, 2, .. . , n, j=1, 2, . . . , m and i+j=P.

In another exemplary embodiment, a non-transitory computer readablemedium having instructions stored therein that, when executed by one ormore processor, cause the one or more processors to perform a method ofscheduling in a dual core computer, comprising dividing a ready queue ofP processes into a first list of n processes and a second list of mprocesses, where n+m equals P, averaging the burst times of theprocesses in each list, adding the averages to generate a first quantumand subtracting the averages to generate a second quantum, assigning thefirst quantum to a first CPU of the dual core computer; and assigningthe second quantum to a second CPU of the dual core computer.

The foregoing general description of the illustrative embodiments andthe following detailed description thereof are merely exemplary aspectsof the teachings of this disclosure, and are not restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of this disclosure and many of theattendant advantages thereof will be readily obtained as the samebecomes better understood by reference to the following detaileddescription when considered in connection with the accompanyingdrawings, wherein:

FIG. 1 illustrates processes in a dual core computing system.

FIG. 2A, 2B are a flowchart of Algorithm 1.

FIG. 2C illustrates the Gantt chart of Algorithm 1.

FIG. 2D illustrates the simulation of Algorithm 2.

FIG. 3A, 3B are a flowchart of Algorithm 1.

FIG. 3C illustrates the Gantt chart of Algorithm 2.

FIG. 3D illustrates the simulation of Algorithm 2.

FIG. 4A is a graph depicting the average waiting time comparison betweenalgorithm 1 and the round robin algorithm.

FIG. 4B is a graph depicting the average turnaround time comparisonbetween algorithm 1 and the round robin algorithm.

FIG. 5A is a graph depicting the average waiting time comparison betweenalgorithm 2 and the round robin algorithm.

FIG. 5B is a graph depicting the average turnaround time comparisonbetween algorithm 2 and the round robin algorithm.

FIG. 6 illustrates a dual core scheduling environment.

FIG. 7 is an illustration of a non-limiting example of details ofcomputing hardware used in the computing system, according to certainembodiments.

FIG. 8 is an exemplary schematic diagram of a data processing systemused within the computing system, according to certain embodiments.

FIG. 9 is an exemplary schematic diagram of a processor used with thecomputing system, according to certain embodiments.

FIG. 10 is an illustration of a non-limiting example of distributedcomponents which may share processing with the controller, according tocertain embodiments.

DETAILED DESCRIPTION

In the drawings, like reference numerals designate identical orcorresponding parts throughout the several views. Further, as usedherein, the words “a,” “an” and the like generally carry a meaning of“one or more,” unless stated otherwise. The drawings are generally drawnto scale unless specified otherwise or illustrating schematic structuresor flowcharts.

Furthermore, the terms “approximately,” “approximate,” “about,” andsimilar terms generally refer to ranges that include the identifiedvalue within a margin of 20%, 10%, or preferably 5%, and any valuestherebetween.

The term “quantum” refers to the period of time for which a process isallowed to run uninterrupted in a preemptive multitasking operatingsystem.

The term “time slice” refers to a short interval of time allotted toeach user or program in a multitasking or timesharing system. Timeslices are typically in milliseconds.

The term “ready list” or “run queue” keeps a list of all processes thatare ready to run. Each of these processes is assigned a “burst time”.

The term “burst time” refers to the amount of time needed to run aprocess in the ready list.

The term “turnaround time” is the total time the CPU takes to completeexecution of a process that is assigned to it by the scheduler.

The term “waiting time” is the time a process stays in a waiting state,residing in the ready queue, before it is assigned to the CPU.

The term “response time” is the time measured from when the processrequests the CPU for the first time; i.e., the process submits itsrequest for the CPU upon the first response it receives from the CPU.

Aspects of this disclosure are directed to a scheduling method for usein process scheduling in a dual core computer, a scheduling system foruse in a dual core computer, and a non-transitory computer readablemedium having instructions stored therein that, when executed by one ormore processor, cause the one or more processors to perform a method ofscheduling in a dual core computer.

Most computing systems have a large number of processes with short CPUbursts interspersed between I/O requests and a small number of processeswith long CPU bursts. To provide good time-sharing performance, arunning process may be preempted to let another one run.

The ready list in the operating system keeps a list of all processesthat are ready to run and are not blocked at input/output or by ablocking system request. The entries in this list are pointers to aprocess control block, which stores all information and states of aprocess. A “ready” process is one which has been loaded into main memoryand is awaiting execution on a CPU (to be context switched onto the CPUby the dispatcher, or a short-term scheduler). There may be many “ready”processes at any one point of the system's execution. For example, in aone-processor system, only one process can execute at any one time, andall other “concurrently executing” processes must wait for execution.When an I/O request for a process is complete, the process moves fromthe waiting state to the ready state and gets placed on a ready queue.

CPU scheduling is the job of a scheduler residing inside a CPU, called ashort-term scheduler or just a CPU scheduler. The CPU scheduler selectsa process from the ready queue and assigns it to CPU when CPU becomesidle. The scheduler makes decisions about the processes based on certainconditions when the process switches between different states asfollows:

i. Running to waiting: The current process goes from the running stateto the waiting state because it issues an I/O request or some operatingsystem request that cannot be satisfied immediately.

ii. Running to ready: A timer interrupt causes the scheduler to run anddecide that a process has run for its allotted interval of time and itis time to move the process from the running state to the ready state.

iii. Waiting to ready: An I/O operation is complete for a process thatrequested it and the process now moves from the waiting to the readystate. The scheduler may then decide to preempt the currently-runningprocess and move this newly-ready process into the running state.

iv. Process terminates.

CPU schedulers use CPU scheduling algorithms specially designed for thescheduling of the processes. Different CPU scheduling algorithms havedifferent characteristics.

Selection of an algorithm may prioritize one process over the other.Throughout its life, a process keeps moving between different queues.The process switches between a ready queue and the input/output (I/O)queue. The ready queue contains the processes that are ready for theCPU, while the I/O queue contains those processes which are waiting foran input/output device response.

CPU scheduling is divided into two major types; preemptive schedulingand non-preemptive scheduling. Non-preemptive conditions occur when theprocess stops, terminates or transits from its running state to thewaiting state. Preemptive scheduling conditions occur when the processchanges its state from running to ready or from waiting to ready. Ascheduler is a preemptive scheduler if it has the ability to get invokedby an interrupt and move a process out of a running state to let anotherprocess run. If a scheduler cannot take the CPU away from a process thenit is a cooperative, or non-preemptive scheduler. Aspects of the presentdisclosure use a preemptive scheduling algorithm.

When a process is first created, it occupies the “created” or “new”state. In this state, the process awaits admission to the “ready” state.Admission will be approved or delayed by a long-term, or admission,scheduler. Typically in most desktop computer systems, this admissionwill be approved automatically. However, for real-time operating systemsthis admission may be delayed. In a real-time system, admitting too manyprocesses to the “ready” state may lead to oversaturation andover-contention of the system's resources, resulting in an inability tomeet process deadlines.

Modern computers are capable of running many different programs orprocesses at the same time. A single core computer having only one CPUis only capable of handling one process at a time.

Dual core environments optimize the computing performance bymultitasking. In the present disclosure, two CPU scheduling techniquesbased on a relative time quantum are presented. The time quantum iscalculated by taking the average of the process burst time for each halfof a ready queue list and then applying addition and/or subtraction tothe relative values. One CPU is directed to use a scheduling techniquehaving a quantum based on the added values while other is directed touse a scheduling technique having a quantum based on the subtractedvalues. Thus, a dual core may run two processes simultaneously, eachbased on different scheduling techniques.

In an aspect of the present disclosure, two different CPU algorithms areused to schedule processing in a dual core environment. In conventionalround robin scheduling, the time quantum is assigned randomly. In thepresent disclosure, a modification of round robin scheduling is used inwhich the ready list is divided into two portions, the burst times areaveraged for each list, then the relative (averaged values) values areadded (Algorithm 1) and subtracted (Algorithm 2) to generate a first andsecond time quantum as described below. A time quantum is assigned toeach process and a CPU is designated to handle the process. In a dualcore processor, one CPU is assigned to use scheduling based on anaddition technique while other is assigned to use scheduling based on asubtraction technique. As a result, the performance of the processing isimproved in terms of average waiting and turnaround time in comparisonto traditional round robin scheduling techniques.

As illustrated in FIG. 1, the ready queue 150 is divided into two lists.One list will be assigned to CPU₁ while the other list will be assignedto CPU₂. The list may be divided in half or one list may have moreprocesses than the other. In general, the list may be divided roughly inhalf by the order of the processes in the queue. Each process has apredetermined burst time. The burst times of the processes in each listare summed and averages of the burst times are calculated i.e. average₁152, (average of burst times of all processes in CPU₁) and average₂ 154(average of burst times of all processes in CPU₂). In CPU₁, the timeslice is calculated based on summing both averages, i.e.average₁+average₂, while in CPU₂, the time slice is calculated based onsubtraction, i.e. average₁−average₂. Based on this calculated timeslice, a first requested process (P1) from list 1 will move into therunning state in CPU₁ and a first requested process (P5) from list 2will move into the running state in CPU₂. After execution, if theremaining burst time of either of the processes is greater than the timeslice of the CPU in which it is running, the process is added to thetail of the queue of its respective list, otherwise the process willexit. In the situation in which an I/O interruption or event occurs, theprocess goes into the waiting state. After I/O or event completion, theprocess will again be added to the ready queue. Although only eightprocesses are shown in FIG. 1, the number of processes is not limited toeight, and new processes may be continuously added to the process queue.However, each original list fully processes before the timeslice isrecalculated with the newly added processes.

The above technique is preemptive. The scheduler can use the summingtechnique on both cores, the subtracting technique on both cores or thesumming technique on a first core and the subtracting techniques on asecond core.

The left side of FIG. 1 illustrates using Algorithm 1, which describesthe summing technique to generate the time quantum. The right side ofFIG. 1 illustrates using Algorithm 2, which describes the subtractiontechnique to generate the time quantum. Both of these algorithms aredescribed in more detail below. Although Algorithm 1 and Algorithm 2 areapplied to a dual core processor in the current aspect, either algorithmmay be used in a single core processor.

The summing aspect for the above technique is shown by the pseudo codeshown in Algorithm 1.

Algorithm 1 sumlist1←0 sumlist2←0 avg1←0 avg2←0 quantum←0 m←length/2avg1←sumlist1/m avg2←sumlist2/(n−m) quantum←avg1+avg2 sum←0 AvgWait←0AvgTurn←0 DO FOR i←0 to length if bursttime[i] > quantum thenbursttime[i] −=quantum FOR j ←0 to length Then if j! = i &&bursttime[j]! = 0 Then waitingtime[j]+=quantum ELSE FOR j ←0 to lengthThen if j!= i && bursttime[j]! = 0 Then waitingtime[j]+=bursttime[i]bursttime[i]←0 FOR k←0 to length sum←sum+bursttime[k] while sum !=0 FORl←0 to length turnaroundtime[i]←waitingtime[i]+process[i] FOR j ←0 tolength AvgWait+=waitingtime [j] FOR j ←0 to lengthAv|gTurn+=turnaroundtime[j]where len=burst time array, q=timeslice, wt(j)=waiting time array,tat[]=turn around time array, process[]=processes array.

Algorithm 1 works by dividing the list of processes present in the readyqueue roughly into halves to form two lists. The relative value of theburst times of each list is then calculated based on its average. Thesum of the average from each of the two lists will be the time quantumfor each process. When the process is assigned to a CPU it will run onlyfor the time equal to the time quantum. In RR (Round Robin), when thetime quantum expires, the CPU switches to the next process. In algorithm1, as the timeslice expires, context switching will occur and the CPUwill be assigned to the next job in the queue. Thus, this algorithm alsosolves the problem of starvation in the shortest job algorithm, as theCPU is not given to the jobs that have greater burst time for a longtime.

A flowchart illustrating the steps of Algorithm I is shown in FIG. 2A,2B and described below.

Step 202: Access the list of processes and respective burst times whichare ready to be assigned to the CPU.

Step 206: Divide the list into halves.

Step 208: Calculate the relative value which is the average value of theburst times in list 1 to obtain AVG1.

Step 210: Calculate the relative value which is the average value of theburst time in list 2 to obtain AVG2.

Step 212: Sum AVG1 and AVG2 to get one specific value and assign thisvalue to the time quantum.

Step 214: Initialize the waiting time of each process as zero.

Step 216: Assign the time quantum to each process, and then take thetime slice for each process.

Step 218: Start with the first process in the queue.

Step 220: When the time quantum of the first process expires, assign theCPU to the next process in the ready queue (context switching).

Steps 220-228: This process continues, until all processes finish.

A non-limiting example of using algorithm 1 is now described using bursttimes from Table 1.

TABLE I Processes and their burst time. Process Burst time P1 2 P2 22 P35 P4 3 P5 2

Step No. 1: Divide the list given in Table I into two portions. List 1will contain processes P1 and P2, while list 2 contains processes P3, P4and P5.

Step No. 2: Calculate the relative value of each list by averaging theburst times of the processes in the list. In this case relative valueswill be r1=12 and r2=3 respectively.

Step No. 3: Sum the relative values to obtain time quantum q such thatq=r1+r2. In this example, q=15.

Step No. 4: Assign the time quantum to each process and assign the CPUto run the first process in the ready queue.

Step No. 5: Waiting time for each process:

P1: 0

P2: 12

P3: 17

P4: 22

P5: 25

Average waiting time: (0+12+17+22+25)/5=15.2

Average Turnaround Time: (2+34+22+25+27)/5=22

FIG. 2C shows the Gantt chart for this example of using Algorithm 1.

Algorithm 1 was implemented in C# using a visual studio program. Thewaiting and turnaround times for each process were calculated and thenaverage waiting and average turnaround times were calculated. Theresults are shown in FIG. 2D.

Algorithm 2 describes the subtraction technique to generate the timequantum. Algorithm 2 works similarly to Algorithm 1, in which the listof processes present in the ready queue are divided into two halves.Again, the relative value of each list is calculated separately based onits average. However, the time quantum is calculated differently. InAlgorithm 2, the value of time quantum is the difference of the twoaverages. The pseudo code for the subtraction aspect is shown below.

Algorithm 2 sumlist1←0 sumlist2←0 avg1←0 avg2←0 quantum←0 m←length/2avg1←sumlist1/m avg2←sumlist2/(n−m) quantum←avg1−avg2 sum←0 AvgWait←0AvgTurn←0 DO FOR i←0 to length if bursttime[i] > quantum thenbursttime[i] −=quantum FOR j←0 to length Then if j! = i && bursttime[j]!= 0 Then waitingtime[j]+=quantum ELSE FOR j←0 to length Then if j! = i&& bursttime[j]! = 0 Then waitingtime[j]+=bursttime[i] bursttime[i]←0FOR k←0 to length sum←sum+bursttime[k] while sum !=0 FOR l←0 to lengthturnaroundtime[i] ←waitingtime[i]+process[i] FOR j ←0 to lengthAvgWait+=waitingtime [j] FOR j ←0 to length AvgTurn+= turnaroundtime[j]

A flowchart illustrating the steps of Algorithm 2 is shown in FIG. 3A,3B and described below.

Step 332: Access the list of processes and respective burst times whichare ready to be assigned to the CPU.

Step 334: Divide the list into halves.

Step 336: Calculate the relative value which is the average value of theburst times in list1 to obtain AVG1.

Step 338: Calculate the relative value which is the average value of theburst time in list2 to obtain AVG2.

Step 340: Subtract AVG2 from AVG1 to get one specific value and assignthis value to the time quantum.

Step 344: Initialize the waiting time of each process as zero.

Step 346: Assign the time quantum to each process, and then take thetime slice for each process.

Step 348: Start with the first process in the queue.

Step 332: When the time quantum of the first process expires, assign theCPU to the next process in the ready queue (context switching).

Step 332: This process continues, until all processes finish.

A non-limiting example of using algorithm 1 is now described using bursttimes from Table 1. The Gantt chart is shown in FIG. 3C.

Step No. 1: Divide the list given in Table I into two portions. List 1will contain processes P1 and P2, while list 2 contains processes P3, P4and P5.

Step No. 2: Calculate the relative value of each list by averaging theburst times of the processes in the list. In this case relative valueswill be r1=12 and r2=3 respectively.

Step No. 3: Subtract the relative values to get time quantum q such as;q=r2−r2. In this example, q=9.

Step No. 4: Assign the time quantum to each process and assign the CPUto run the first process in the ready queue.

Step No. 5: Waiting time for each process:

P1: 0

P2: 12

P3: 11

P4: 16

P5: 19

Average waiting time: (0+12+11+16+19)/5=11.6

Average Turnaround Time: (2+34+16+19+21)/5=18

Simulation results are shown in FIG. 3D showing the results for thecalculations of the waiting and turnaround times and their averages.

The simulation results for both algorithm 1 and algorithm 2 werecompared with results using the Round Robin algorithm. All threealgorithms were implemented in C# using a visual studio program.Simulation of the three algorithms was created by assigning a number ofsimulated number of processes and gradually increasing this number ofprocesses. FIG. 4A show the average waiting times using Algorithm 1 ascompared with the average waiting times using the Round Robin algorithm.As shown in the figure, the initial number of processes was 10 and thisnumber was gradually increased to 5000. FIG. 4B shows where the numberof processes was increased to 100000. Random burst times were assignedto each process. For consistency, the same numbers of processes andburst times are applied in comparing three algorithms. On the y-axes,the average waiting times (FIG. 4A, 5A) and average turnaround times(FIG. 4B, 5B) are plotted. The results are as follows:

Average Waiting Time

The numbers of processes were plotted on the x-axis, while waiting timewas plotted on the y-axis in FIG. 4A, 5A. Referring to FIG. 4A, it isshown that average waiting times (PA) using Algorithm 1 are less thanaverage waiting times (RR) using the traditional round robin algorithm.This means that processes have to wait less time in the ready queue whenusing the Algorithm 1 technique. Referring to FIG. 5A, Algorithm 2 showssimilar performance to the traditional round robin algorithm at lowerprocess numbers. As the number of processes increases Algorithm 2performs better than the round robin algorithm, showing less averagewaiting time.

Average Turnaround Time

FIG. 4B, 5B are plots which compare the average turnaround time forAlgorithms 1 and 2 with the Round Robin algorithm. The numbers ofprocesses are on the x-axis, while turnaround time is plotted on they-axis. FIG. 4B shows that Algorithm 1 produces significantly loweraverage turn around time than does the Round Robin algorithm. Althoughthe average turn around time using Algorithm 2 is approximately the sameas that of the Round Robin algorithm for lower process numbers, highprocess numbers show some improvement in turn around time as shown inFIG. 5B.

FIG. 6 illustrates a dual core computer system which may use Algorithms1 and 2 to schedule processes. FIG. 6 shows an I/O device 660 connectedto a ready queue 620, which receives processes from the I/O device. Adivider 631 is connected to the ready queue 620 to receive theprocesses. The divider divides the ready queue list of processes roughlyin half and sends a first list, L₁, and a second list, L₂, to anaverager 633. The averager outputs a first and second average, Avg₁ andAvg² respectively. Both averages are sent to the summing module 634 andtheir sum is output as a first quantum, q₁ to a first CPU₁. Bothaverages are also sent to the subtraction module 635, where the absolutevalue of their difference is output as a second quantum, q₂, to a secondCPU₂. An assignment module 632 transmits each process in the first listL₁ to CPU₁, where it runs until it terminates or for the amount of time,q₁. The output, O_(i) and the burst time, B_(i) for each _(i)th processin L₁ is sent to comparator 636. The comparator determines if theprocess has terminated, in which case it sends Oi to the I/O device 660.The comparator compares each burst time, Bi, to the quantum q₁. If theburst time is greater than the quantum, the remaining process R_(i) issent to be added to the tail of L₁ to complete processing. Similarly,the assignment module 632 transmits each process in the second list L₂to CPU₂, where it runs until it terminates or for the amount of time,q₂. The output, O_(j) and the burst time, B_(j) for each _(j)th processin L₂ is sent to comparator 636. The comparator determines if theprocess has terminated, in which case it sends Oj to the I/O device 660.The comparator compares each burst time, Bj, to the quantum q₂. If theburst time is greater than the quantum, the remaining process R_(j) issent to be added to the tail of L₂ to complete processing.

The first embodiment is illustrated in FIGS. 1, 2A, 2B, 3A, 3B and 6.The first embodiment describes a scheduling method for use in processscheduling in a dual core computer 600, comprising dividing (see Divider631, FIG. 6), by a scheduler 630 having circuitry including programinstructions configured for calculating, a ready queue 620 of Pprocesses into a first list of n processes, P(n), and a second list of mprocesses, P(m), wherein each process in each list has a preassignedburst time and n+m=P; averaging (See average 633) the burst times of then processes in the first list to generate a first relative value, Avg₁;averaging the burst times of the m processes in the second list togenerate a second relative value Avg₂; adding (See summing module 634)the first relative value and the second relative value to generate afirst quantum, q₁; subtracting (see subtraction module 635) the smallerof the relative values from the larger of the relative values togenerate a second quantum, q₂; assigning (see assignment module 632), bya scheduler 630 having program instructions configured for assigningquanta to the cores of the dual core computer, the first quantum q₁ to afirst CPU₁ 640; and assigning the second quantum q₂ to a second CPU₂642.

The method further comprises assigning, by the scheduler, a processP_(i)(n) of the first list to the first CPU₁, where i=1, 2, . . . , n asshown in FIG. 1 and FIG. 6; comparing, by using a comparator 636 of thecircuitry, the burst time of the process P_(i)(n) to the first quantumq₁. If the burst time of the process P_(i)(n) is less than the firstquantum, running, by CPU₁, the process P_(i)(n) to generate an output,O_(i) and if the burst time of the process P_(i)(n) is greater than thefirst quantum, running the process P_(i)(n) for a time equal to thefirst quantum, and adding a remaining burst time of the process P_(i)(n)to a tail of the first list (see the Yes arrow pointing to the P4 in theready queue 150, FIG. 1).

The method continues by assigning, by the scheduler, a process P_(j)(m)of the second list to the second CPU₂, where j=1, 2, . . . , m;comparing, by using a comparator 636 of the circuitry, the burst time ofthe process P_(j)(m) of the second list to the second quantum q₂; if theburst time of the process P_(j)(m) is less than the second quantum,running, by CPU₂, the process P_(j)(m) to generate an output, O_(j); ifthe burst time of the process P_(j)(m) is greater than the secondquantum, running the process P_(j)(m) for a time equal to the secondquantum, and adding a remaining burst time of the process P_(j)(m) to atail of the second list (see the Yes arrow pointing to the P8 in theready queue 150, FIG. 1).

The method iterates the above procedure by assigning, by the scheduler,a second process, P_(i+1)(n), to CPU₁; running the second process,P_(i+1)(n), until either the process ends and generates an outputO_(i+1) or the quantum q₁ expires; transmitting the output O_(i+1) to anI/O port 660 if the process ends or adding the remainder of the secondprocess, P_(i+1)(n), to the tail of the first list if the quantum q₁expires; then assigning each next process of the first list to CPU₁,running each next process of the first list, transmitting either theoutput to an I/O port or adding a remainder of next process to the tailof the first list, until O_(n) outputs are generated. When O_(n) outputshave been received at I/O port 660, the first list has been processed.

Similarly as for the first list, the method includes assigning, by thescheduler, a second process, P_(j+1)(m), to CPU₂; running the secondprocess, P_(j+1)(m), until either the process ends and generates anoutput O_(j+1) or the quantum q₂ expires; transmitting the outputO_(j+1) to an I/O port 660 if the process ends; adding the remainder ofthe second process, P_(j+1)(m), to the tail of the second list if thequantum q₂ expires; then assigning each next process of the second listto CPU₂, running each next process of the second list, and transmittingeither the output to an I/O port or adding a remainder of next processto the tail of the second list, until O_(m) outputs are generated. WhenO_(m) outputs have been received at I/O port 660, the second list hasbeen processed.

The method continues by assigning, by the assignment module 632 ofscheduler 630, a first process P₁(n) of the first list to the firstCPU₁; simultaneously assigning, by the scheduler, a first process P₁(m)of the second list to the second CPU₂; comparing, by using a comparator636 of the circuitry, the burst time of the process P₁(n) to the firstquantum q₁. If the burst time of the process P₁(n) is less than thefirst quantum, running, by CPU₁, the process P₁(n) to generate anoutput, O₁(n) and if the burst time of the process P₁(n) is greater thanthe first quantum, running the process P₁(n) for a time equal to thefirst quantum, adding a remaining burst time of the process P₁(n) to atail of the first list, and assigning a second process P₂(n) from thefirst list to CPU₁; comparing, by using the comparator, the burst timeof the process P₁(m) of the second list to the second quantum q₂. If theburst time of the process P₁(m) is less than the second quantum,running, by CPU₂, the process P₁(m) to generate an output, O_(j)(m) andif the burst time of the process P₁(m) is greater than the secondquantum, running the process P₁(m) for a time equal to the secondquantum, adding a remaining burst time of the process P₁(m) to a tail ofthe second list, and assigning a second process P₂(m) from the secondlist to CPU₂.

The method iterates by assigning each next process P_(i)(n) of the firstlist to CPU₁; running each next process P_(i)(n); if P_(i)(n)terminates, transmitting the output O_(i)(n) to an I/O port; if P_(i)(n)does not terminate, adding a remainder of P_(i)(n) to the tail of thefirst list;

continuing to assign and run each next process until O_(n) outputs aregenerated; assigning each next process P_(j)(m) of the second list toCPU₂; running each next process P_(j)(m); if P_(j)(m) terminates,transmitting the output O_(j)(m) to an I/O port; if P_(j)(m) does notterminate, adding a remainder of P_(j)(m) to the tail of the second listand continuing to assign and run each next process until O_(m) outputsare generated.

The second embodiment is illustrated in FIGS. 1, 2A, 2B, 3A, 3B and 6.The second embodiment describes a scheduling system for use in a dualcore computer 600, comprising an input/output device, I/O 660, whereinthe I/O device receives process requests and outputs processing results;a ready queue 620, wherein the ready queue receives processes P from theI/O device, each process having a predetermined burst time, B; ascheduler 610 including: a divider 630, wherein the divider hascircuitry configured to divide the ready queue into two roughly equalportions and outputs the portions as a first list and a second list; anaverage 632 having circuitry configured to average the burst time of theprocesses in the first and second lists to generate a first relativevalue Avg₁ and a second relative value Avg₂ respectively; a summingmodule 634 having circuitry configured to add the first relative valueand the second relative value and generate a first quantum, q₁; asubtraction module 636 having circuitry configured to determine theabsolute value of the difference between the relative values andgenerate a second quantum q₂; and an assignment module 632 for assigninga process P_(i)(n) from the first list to a first CPU₁ 610 and a processP_(j)(m) from the second list to a second CPU₂ 642, where i=1, 2, . . ., n, j=1, 2, . . . , m and i+j=P. The lists can be any portion of theready queue. For example, for a ready queue containing 100 processes,the first list may contain 50 processes (n=50) and the second list maycontain 50 processes (m=50). However, the first list may have 25processes and the second list 75 processes. The designation of n and mand the total number of processes P depends on the types of processes,the overhead of the computing system and other design parameters of thecomputer and is not limited by the above example. FIG. 4A, 5A shows arange of 0 to 5000 processes which were simulated and FIG. 4B, 5B showsa range of 0 to 10000 processes using the method above. Note that FIG.4A, 4B, 5A, 5B demonstrate that the method and system detailed abovesuccessfully decreases the average waiting times and turn around timesof the processing.

The scheduling system further includes a comparator 636 having circuitryconfigured to receive an output O_(i)(n)and the burst time B_(i)(n) foreach P_(i)(n) from the first CPU₁, compare the burst time B_(i)(n) tothe first quantum, q₁, and determine whether the burst time B_(i)(n) isgreater than the first quantum q₁, and if the burst time B_(i)(n) isgreater than the first quantum q₁, calculate the remaining burst timeR_(i)(n) of the process P_(i)(n) and add the remaining burst timeR_(i)(n) to the tail of the first list (see FIG. 1); and if the bursttime B_(i)(n) is less than the first quantum q₁, transmit the outputO_(i)(n) to the I/O port 660.

Similarly, the comparator further has circuitry configured to receive anoutput O_(j)(m) and the burst time B_(j)(m) for each P_(j)(m) from thesecond CPU₂, compare the burst time B_(j)(m) to the second quantum, q₂,and determine whether the burst time B_(j)(m) is greater than the secondquantum q₂. If the burst time B_(j)(m) is greater than the secondquantum q₂, calculate the remaining burst time R_(j)(m) of the processP_(j)(m) and add the remaining burst time R_(j)(m) to the tail of thesecond list; and if the burst time B_(j)(m) is less than the secondquantum q₂, transmit the output O_(j)(m) to the I/O port.

The assignment module 632 continues to assign each next process P_(i)(n)of the first list to CPU₁ and run each next process P_(i)(n). IfP_(i)(n) terminates, the assignment module transmits the output O_(i)(n)to an I/O port 660 and if P_(i)(n) does not terminate, the assignmentmodule adds a remainder of P_(i)(n) to the tail of the first list (seeFIG. 1). The assignment module continues to assign and run each nextprocess until O_(n) outputs are generated, which indicates the processesof the first list have finished running.

The assignment module assigns each next process P_(j)(m) of the secondlist to CPU₂ and runs each next process P_(j)(m). If P_(j)(m)terminates, the scheduler transmits the output O_(j)(m) to an I/O portand if P_(j)(m) does not terminate, the scheduler adds a remainder ofP_(j)(m) to the tail of the second list. The assignment module continuesto assign and run each next process until O_(m) outputs are generated,which indicates the processes of the second list have finished running.

A comparator 636 connected to CPU1 and CPU2 makes the determination ofwhether an output is sent to an I/O port 660 or a remainder of a processis added to the tail of the first or the second list (as shown in FIG.1).

The assignment module simultaneously assigns a first process P₁(n) fromthe first list to the first CPU₁ and a first process P₁(m) from thesecond list to the second CPU₂, so that the processing of the two listsruns concurrently.

The third embodiment is illustrated in FIGS. 1, 2A, 2B, 3A, 3B and 6.The third embodiment describes a non-transitory computer readable mediumhaving instructions stored therein that, when executed by one or moreprocessor, cause the one or more processors to perform a method ofscheduling in a dual core computer. The non-transitory computer readablemedium method comprises dividing, by a scheduler having circuitryincluding program instructions configured for calculating, a ready queueof P processes into a first list of n processes, P(n), and a second listof m processes, P(m), wherein each process in each list has apreassigned burst time and n+m=P; averaging the burst times of the nprocesses in the first list to generate a first relative value, Avg₁;averaging the burst times of the m processes in the second list togenerate a second relative value Avg₂; adding the first relative valueand the second relative value to generate a first quantum, q₁;subtracting the smaller of the relative values from the larger of therelative values to generate a second quantum, q₂; assigning, by ascheduler having program instructions configured for assigning quanta tothe cores of the computing system, the first quantum q₁ to a first CPU₁of the dual core computer; and assigning the second quantum q₂ to asecond CPU₂ of the dual core computer.

The non-transitory computer readable medium method further comprisesassigning, by the scheduler, a process P_(i)(n) of the first list to thefirst CPU₁, where i=1, 2, . . . , n; comparing, by using a comparator ofthe circuitry, the burst time of the process P_(i)(n) to the firstquantum q₁. If the burst time of the process P_(i)(n) is less than thefirst quantum, running, by CPU₁, the process P_(i)(n) to generate anoutput, O_(i) and if the burst time of the process P_(i)(n) is greaterthan the first quantum, running the process P_(i)(n) for a time equal tothe first quantum, and adding a remaining burst time of the processP_(i)(n) to a tail of the first list.

The non-transitory computer readable medium method further comprisesassigning, by the scheduler, a process P,(m) of the second list to thesecond CPU₂, where j=1, 2, . . . , m; comparing, by using a comparatorof the circuitry, the burst time of the process P_(j)(m) of the secondlist to the second quantum q₂; if the burst time of the process P_(j)(m)is less than the second quantum, running, by CPU₂, the process P_(j)(m)to generate an output, O_(j); if the burst time of the process P_(j)(m)is greater than the second quantum, running the process P_(j)(m) for atime equal to the second quantum, and adding a remaining burst time ofthe process P_(j)(m) to a tail of the second list.

The non-transitory computer readable medium method continues byassigning, by the scheduler, a second process, P_(i+1)(n), to CPU₁;running the second process, P_(i+1)(n), until either the process endsand generates an output O_(i+1) or the quantum q₁ expires; transmittingthe output O_(i+1) to an I/O port if the process ends; adding theremainder of the second process, P_(i+1)(n), to the tail of the firstlist; assigning each next process of the first list to CPU₁, runningeach next process of the first list, transmitting either the output toan I/O port or adding a remainder of next process to the tail of thefirst list, until O_(n) outputs are generated.

The non-transitory computer readable medium method further continues byassigning, by the scheduler, a second process, P_(j+1)(m), to CPU₂;running the second process, P_(j+1)(m), until either the process endsand generates an output O_(j+1) or the quantum q₂ expires;

transmitting the output O_(j+1) to an I/O port if the process ends;adding the remainder of the second process, P_(j+1)(m), to the tail ofthe second list; assigning each next process of the second list to CPU₂,running each next process of the second list, and transmitting eitherthe output to an I/O port or adding a remainder of next process to thetail of the second list, until O_(m) outputs are generated.

The non-transitory computer readable medium method further continues byassigning, by the scheduler, a first process P₁(n) of the first list tothe first CPU₁; simultaneously assigning, by the scheduler, a firstprocess P₁(m) of the second list to the second CPU₂; comparing, by usinga comparator of the circuitry, the burst time of the process P₁(n) tothe first quantum q₁. If the burst time of the process P₁(n) is lessthan the first quantum, running, by CPU₁, the process P₁(n) to generatean output, O₁(n) and if the burst time of the process P₁(n) is greaterthan the first quantum, running the process P₁(n) for a time equal tothe first quantum, adding a remaining burst time of the process P₁(n) toa tail of the first list, and assigning a second process P₂(n) from thefirst list to CPU₁; and comparing, by using the comparator, the bursttime of the process P₁(m) of the second list to the second quantum q₂.If the burst time of the process P₁(m) is less than the second quantum,running, by CPU₂, the process P₁(m) to generate an output, O_(j)(m) andif the burst time of the process P₁(m) is greater than the secondquantum, running the process P₁(m) for a time equal to the secondquantum, adding a remaining burst time of the process P₁(m) to a tail ofthe second list, and assigning a second process P₂(m) from the secondlist to CPU₂.

The non-transitory computer readable medium method further continues byassigning each next process P_(i)(n) of the first list to CPU₁; runningeach next process P_(i)(n); if P_(i)(n) terminates, transmitting theoutput O_(i)(n) to an I/O port; if P_(i)(n) does not terminate, adding aremainder of P_(i)(n) to the tail of the first list; continuing toassign and run each next process until O_(n) outputs are generated;assigning each next process P_(j)(m) of the second list to CPU_(2;)

running each next process P_(j)(m) and if P_(j)(m) terminates,transmitting the output O_(j)(m) to an I/O port.

The present disclosure presents two variations of the round robinalgorithm, which improve the performance of traditional round robinapproach in terms of average waiting and average turnaround time ofprocesses.

Next, further details of the hardware description of the computingenvironment of FIG. 6 according to exemplary embodiments is describedwith reference to FIG. 7. In FIG. 7, a controller 700 is described isrepresentative of dual core computing system 600 of FIG. 6 in which thecontroller is a computing device which includes a first CPU 701 and asecond CPU 703 which performs the processes described above/below. Theprocess data and instructions may be stored in memory 702. Theseprocesses and instructions may also be stored on a storage medium disk704 such as a hard drive (HDD) or portable storage medium or may bestored remotely.

Further, the claimed advancements are not limited by the form of thecomputer-readable media on which the instructions of the inventiveprocess are stored. For example, the instructions may be stored on CDs,DVDs, in FLASH memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk or anyother information processing device with which the computing devicecommunicates, such as a server or computer.

Further, the claimed advancements may be provided as a utilityapplication, background daemon, or component of an operating system, orcombination thereof, executing in conjunction with CPU 701, 703 and anoperating system such as Microsoft Windows 7, UNIT, Solaris, LINU7,Apple MAC-OS and other systems known to those skilled in the art.

The hardware elements in order to achieve the computing device may berealized by various circuitry elements, known to those skilled in theart. For example, CPU 701 or CPU 703 may be a Xenon or Core processorfrom Intel of America or an Opteron processor from AMD of America, ormay be other processor types that would be recognized by one of ordinaryskill in the art. Alternatively, the CPU 701, 703 may be implemented onan FPGA, ASIC, PLD or using discrete logic circuits, as one of ordinaryskill in the art would recognize. Further, CPU 701, 703 may beimplemented as multiple processors cooperatively working in parallel toperform the instructions of the inventive processes described above.

The computing device in FIG. 7 also includes a network controller 706,such as an Intel Ethernet PRO network interface card from IntelCorporation of America, for interfacing with network 760. As can beappreciated, the network 760 can be a public network, such as theInternet, or a private network such as an LAN or WAN network, or anycombination thereof and can also include PSTN or ISDN sub-networks. Thenetwork 760 can also be wired, such as an Ethernet network, or can bewireless such as a cellular network including EDGE, 3G and 4G wirelesscellular systems. The wireless network can also be WiFi, Bluetooth, orany other wireless form of communication that is known.

The computing device further includes a display controller 708, such asa NVIDIA GeForce GT7 or Quadro graphics adaptor from NVIDIA Corporationof America for interfacing with display 710, such as a Hewlett PackardHPL2445w LCD monitor. A general purpose I/O interface 712 interfaceswith a keyboard and/or mouse 714 as well as a touch screen panel 716 onor separate from display 710. General purpose I/O interface alsoconnects to a variety of peripherals 718 including printers andscanners, such as an OfficeJet or DeskJet from Hewlett Packard.

A sound controller 720 is also provided in the computing device such asSound Blaster 7-Fi Titanium from Creative, to interface withspeakers/microphone 722 thereby providing sounds and/or music.

The general purpose storage controller 724 connects the storage mediumdisk 704 with communication bus 726, which may be an ISA, EISA, VESA,PCI, or similar, for interconnecting all of the components of thecomputing device. A description of the general features andfunctionality of the display 710, keyboard and/or mouse 714, as well asthe display controller 708, storage controller 724, network controller706, sound controller 720, and general purpose I/O interface 712 isomitted herein for brevity as these features are known.

The exemplary circuit elements described in the context of the presentdisclosure may be replaced with other elements and structureddifferently than the examples provided herein. Moreover, circuitryconfigured to perform features described herein may be implemented inmultiple circuit units (e.g., chips), or the features may be combined incircuitry on a single chipset, as shown on FIG. 8.

FIG. 8 shows a schematic diagram of a data processing system, accordingto certain embodiments, for performing the functions of the exemplaryembodiments. The data processing system is an example of a computer inwhich code or instructions implementing the processes of theillustrative embodiments may be located.

In FIG. 8, data processing system 800 employs a hub architectureincluding a north bridge and memory controller hub (NB/MCH) 825 and asouth bridge and input/output (I/O) controller hub (SB/ICH) 820. Thecentral processing unit (CPU) 830 is connected to NB/MCH 825. The NB/MCH825 also connects to the memory 845 via a memory bus, and connects tothe graphics processor 850 via an accelerated graphics port (AGP). The

NB/MCH 825 also connects to the SB/ICH 820 via an internal bus (e.g., aunified media interface or a direct media interface). The CPU Processingunit 830 may contain one or more processors and even may be implementedusing one or more heterogeneous processor systems. For example, FIG. 9shows one implementation of CPU 830. In one implementation, theinstruction register 938 retrieves instructions from the fast memory940. At least part of these instructions are fetched from theinstruction register 938 by the control logic 936 and interpretedaccording to the instruction set architecture of the CPU 830. Part ofthe instructions can also be directed to the register 932. In oneimplementation the instructions are decoded according to a hardwiredmethod, and in another implementation the instructions are decodedaccording a microprogram that translates instructions into sets of CPUconfiguration signals that are applied sequentially over multiple clockpulses. After fetching and decoding the instructions, the instructionsare executed using the arithmetic logic unit (ALU) 934 that loads valuesfrom the register 932 and performs logical and mathematical operationson the loaded values according to the instructions. The results fromthese operations can be feedback into the register and/or stored in thefast memory 940. According to certain implementations, the instructionset architecture of the CPU 830 can use a reduced instruction setarchitecture, a complex instruction set architecture, a vector processorarchitecture, a very large instruction word architecture. Furthermore,the CPU 830 can be based on the Von Neuman model or the Harvard model.The CPU 830 can be a digital signal processor, an FPGA, an ASIC, a PLA,a PLD, or a CPLD. Further, the CPU 830 can be an x86 processor by Intelor by AMD; an ARM processor, a Power architecture processor by, e.g.,IBM; a SPARC architecture processor by Sun Microsystems or by Oracle; orother known CPU architecture. Referring again to FIG. 8, the dataprocessing system 800 can include that the SB/ICH 820 is coupled througha system bus to an I/O Bus, a read only memory (ROM) 856, universalserial bus (USB) port 864, a flash binary input/output system (BIOS)868, and a graphics controller 858. PCI/PCIe devices can also be coupledto SB/ICH 888 through a PCI bus 862. The PCI devices may include, forexample, Ethernet adapters, add-in cards, and PC cards for notebookcomputers. The Hard disk drive 860 and CD-ROM 866 can use, for example,an integrated drive electronics (IDE) or serial advanced technologyattachment (SATA) interface. In one implementation the I/O bus caninclude a super I/O (SIO) device.

Further, the hard disk drive (HDD) 860 and optical drive 866 can also becoupled to the SB/ICH 820 through a system bus. In one implementation, akeyboard 870, a mouse 872, a parallel port 878, and a serial port 876can be connected to the system bus through the I/O bus. Otherperipherals and devices that can be connected to the SB/ICH 820 using amass storage controller such as SATA or PATA , an Ethernet port, an ISAbus, a LPC bridge, SMBus, a DMA controller, and an Audio Codec.

Moreover, the present disclosure is not limited to the specific circuitelements described herein, nor is the present disclosure limited to thespecific sizing and classification of these elements. For example, theskilled artisan will appreciate that the circuitry described herein maybe adapted based on changes on battery sizing and chemistry, or based onthe requirements of the intended back-up load to be powered.

The functions and features described herein may also be executed byvarious distributed components of a system. For example, one or moreprocessors may execute these system functions, wherein the processorsare distributed across multiple components communicating in a network.The distributed components may include one or more client and servermachines, which may share processing, as shown by FIG. 10, in additionto various human interface and communication devices (e.g., displaymonitors, smart phones, tablets, personal digital assistants (PDAs)).The network may be a private network, such as a LAN or WAN, or may be apublic network, such as the Internet. Input to the system may bereceived via direct user input and received remotely either in real-timeor as a batch process. Additionally, some implementations may beperformed on modules or hardware not identical to those described.Accordingly, other implementations are within the scope that may beclaimed.

The above-described hardware description is a non-limiting example ofcorresponding structure for performing the functionality describedherein. Obviously, numerous modifications and variations of the presentdisclosure are possible in light of the above teachings. It is thereforeto be understood that within the scope of the appended claims, theinvention may be practiced otherwise than as specifically describedherein.

1. A scheduling method for use in process scheduling in a dual core computer, comprising: dividing, by a scheduler having circuitry including program instructions configured for calculating, a ready queue of P processes into a first list of n processes, P(n), and a second list of m processes, P(m), wherein each process in each list has a preassigned burst time and n+m=P; averaging the burst times of the n processes in the first list to generate a first relative value, Avg₁; averaging the burst times of the m processes in the second list to generate a second relative value Avg₂; adding the first relative value and the second relative value to generate a first quantum, q₁; subtracting the smaller of the relative values from the larger of the relative values to generate a second quantum, q₂; assigning, by a scheduler having program instructions configured for assigning quanta to the cores of the dual core computer, the first quantum q₁ to a first CPU₁; and assigning the second quantum q₂ to a second CPU₂.
 2. The scheduling method of claim 1, further comprising assigning, by the scheduler, a process P_(i)(n) of the first list to the first CPU₁, where i=1, 2, . . . , n; comparing, by using a comparator of the circuitry, the burst time of the process P_(i)(n) to the first quantum q₁, if the burst time of the process P_(i)(n) is less than the first quantum, running, by CPU₁, the process P_(i)(n) to generate an output, O_(i); if the burst time of the process P_(i)(n) is greater than the first quantum, running the process P_(i)(n) for a time equal to the first quantum, and adding a remaining burst time of the process P_(i)(n) to a tail of the first list.
 3. The scheduling method of claim 1, further comprising assigning, by the scheduler, a process P_(j)(m) of the second list to the second CPU₂, where j=1, 2, . . . , m; comparing, by using a comparator of the circuitry, the burst time of the process P_(j)(m) of the second list to the second quantum q₂, if the burst time of the process P_(j)(m) is less than the second quantum, running, by CPU₂, the process P_(j)(m) to generate an output, O_(j); if the burst time of the process P_(j)(m) is greater than the second quantum, running the process P_(j)(m) for a time equal to the second quantum, and adding a remaining burst time of the process P_(j)(m) to a tail of the second list.
 4. The scheduling method of claim 2, further comprising assigning, by the scheduler, a second process, P_(i+1)(n), to CPU₁; running the second process, P_(i+1)(n), until either the process ends and generates an output O_(i+1) or the quantum q₁ expires; transmitting the output O_(i+1) to an I/O port if the process ends; adding the remainder of the second process, P_(i+1)(n), to the tail of the first list if the quantum q₁ expires; assigning each next process of the first list to CPU₁, running each next process of the first list, transmitting either the output to an I/O port or adding a remainder of next process to the tail of the first list, until O_(n) outputs are generated.
 5. The scheduling method of claim 3, further comprising assigning, by the scheduler, a second process, P_(j+1)(m), to CPU₂; running the second process, P_(j+1)(m), until either the process ends and generates an output O_(j+1) or the quantum q. expires; transmitting the output O_(j+1) to an I/O port if the process ends; adding the remainder of the second process, P_(j+1)(m), to the tail of the second list if the quantum q₂ expires; assigning each next process of the second list to CPU₂, running each next process of the second list, and transmitting either the output to an I/O port or adding a remainder of next process to the tail of the second list, until O_(m) outputs are generated.
 6. The scheduling method of claim 1, further comprising assigning, by the scheduler, a first process P₁(n) of the first list to the first CPU₁; simultaneously assigning, by the scheduler, a first process P₁(m) of the second list to the second CPU₂; comparing, by using a comparator of the circuitry, the burst time of the process P₁(n) to the first quantum q₁, if the burst time of the process P₁(n) is less than the first quantum, running, by CPU₁, the process P₁(n) to generate an output, O₁(n); if the burst time of the process P₁(n) is greater than the first quantum, running the process P₁(n) for a time equal to the first quantum, adding a remaining burst time of the process P₁(n) to a tail of the first list, and assigning a second process P₂(n) from the first list to CPU₁; comparing, by using the comparator, the burst time of the process P₁(m) of the second list to the second quantum q₂; if the burst time of the process P₁(m) is less than the second quantum, running, by CPU₂, the process P₁(m) to generate an output, O_(j)(m); if the burst time of the process P₁(m) is greater than the second quantum, running the process P₁(m) for a time equal to the second quantum, adding a remaining burst time of the process P₁(m) to a tail of the second list, and assigning a second process P₂(m) from the second list to CPU₂.
 7. The scheduling method of claim 6, further comprising assigning each next process P_(i)(n) of the first list to CPU₁; running each next process P_(i)(n); if P_(i)(n) terminates, transmitting the output O_(i)(n) to an I/O port; if P_(i)(n) does not terminate, adding a remainder of P_(i)(n) to the tail of the first list; continuing to assign and run each next process until O_(n) outputs are generated; assigning each next process P_(j)(m) of the second list to CPU₂; running each next process P_(j)(m); if P_(j)(m) terminates, transmitting the output O_(j)(m) to an I/O port; if P_(j)(m) does not terminate, adding a remainder of P_(j)(m) to the tail of the second list; continuing to assign and run each next process until O_(m) outputs are generated.
 8. A scheduling system for use in a dual core computer, comprising: an input/output device, I/O, wherein the I/O device receives process requests and outputs processing results; a ready queue, wherein the ready queue receives processes P from the I/O device, each process having a predetermined burst time, B; a scheduler including: a divider, wherein the divider has circuitry configured to divide the ready queue into two roughly equal portions and outputs the portions as a first list and a second list; an averager having circuitry configured to average the burst time of the processes in the first and second lists to generate a first relative value Avg₁ and a second relative value Avg₂ respectively; a summing module having circuitry configured to add the first relative value and the second relative value and generate a first quantum, q₁; a subtraction module having circuitry configured to determine the absolute value of the difference between the relative values and generate a second quantum q₂; and an assignment module for assigning a process P_(i)(n) from the first list to a first CPU₁ and a process P_(j)(m) from the second list to a second CPU₂, where i=1, 2, . . . , n, j=1, 2, . . . , m and i+j=P.
 9. The scheduling system of claim 8, further comprising a comparator having circuitry configured to receive an output O_(i)(n)and the burst time B_(i)(n) for each P_(i)(n) from the first CPU₁, compare the burst time B_(i)(n) to the first quantum, q₁, and determine whether the burst time B_(i)(n) is greater than the first quantum q₁; if the burst time B_(i)(n) is greater than the first quantum q₁, calculate the remaining burst time R_(i)(n) of the process P_(i)(n) and add the remaining burst time R_(i)(n) to the tail of the first list; and if the burst time B_(i)(n) is less than the first quantum q₁, transmit the output O_(i)(n) to the I/O port.
 10. The scheduling system of claim 9, comprising the comparator further having circuitry configured to receive an output O_(j)(m) and the burst time B_(j)(m) for each P_(j)(m) from the second CPU₂, compare the burst time B_(j)(m) to the second quantum, q₂, and determine whether the burst time B_(j)(m) is greater than the second quantum q₂; if the burst time B_(j)(m) is greater than the second quantum q₂, calculate the remaining burst time R_(j)(m) of the process P_(j)(m) and add the remaining burst time R_(j)(m) to the tail of the second list; and if the burst time B_(j)(m) is less than the second quantum q₂, transmit the output O_(j)(m) to the I/O port.
 11. The scheduling system of claim 10, wherein the assignment module continues to assign each next process P_(i)(n) of the first list to CPU₁ and run each next process P_(i)(n); wherein, if P_(i)(n) terminates, the assignment module transmits the output O_(i)(n) to an I/O port; if P_(i)(n) does not terminate, the assignment module adds a remainder of P_(i)(n) to the tail of the first list; the assignment module continues to assign and run each next process until O_(n) outputs are generated; assigns each next process P_(j)(m) of the second list to CPU₂ and runs each next process P_(j)(m); if P_(j)(m) terminates, the scheduler transmits the output O_(j)(m) to an I/O port; if P_(j)(m) does not terminate, the scheduler adds a remainder of P_(j)(m) to the tail of the second list; and the assignment module continues to assign and run each next process until O_(m) outputs are generated.
 12. The scheduling system of claim 10, wherein a comparator connected to CPU1 and CPU2 makes the determination of whether an output is sent to an I/O port or a remainder of a process is added to the tail of the first or the second list.
 13. The scheduling system of claim 8, wherein the assignment module simultaneously assigns a first process P₁(n) from the first list to the first CPU ₁and a first process P₁(m) from the second list to the second CPU₂.
 14. A non-transitory computer readable medium having instructions stored therein that, when executed by one or more processor, cause the one or more processors to perform a method of scheduling in a dual core computer, comprising dividing, by a scheduler having circuitry including program instructions configured for calculating, a ready queue of P processes into a first list of n processes, P(n), and a second list of m processes, P(m), wherein each process in each list has a preassigned burst time and n+m=P; averaging the burst times of the n processes in the first list to generate a first relative value, Avg₁; averaging the burst times of the m processes in the second list to generate a second relative value Avg₂; adding the first relative value and the second relative value to generate a first quantum, q₁; subtracting the smaller of the relative values from the larger of the relative values to generate a second quantum, q₂; assigning, by a scheduler having program instructions configured for assigning quanta to the cores of the computing system, the first quantum q₁ to a first CPU₁ of the dual core computer; and assigning the second quantum q₂ to a second CPU₂ of the dual core computer.
 15. The non-transitory computer readable medium method of claim 14, further comprising assigning, by the scheduler, a process P_(i)(n) of the first list to the first CPU₁, where i=1, 2, . . . , n; comparing, by using a comparator of the circuitry, the burst time of the process P_(i)(n) to the first quantum q₁, if the burst time of the process P_(i)(n) is less than the first quantum, running, by CPU₁, the process P_(i)(n) to generate an output, O_(i); if the burst time of the process P_(i)(n) is greater than the first quantum, running the process P_(i)(n) for a time equal to the first quantum, and adding a remaining burst time of the process P_(i)(n) to a tail of the first list.
 16. The non-transitory computer readable medium method of claim 14, further comprising assigning, by the scheduler, a process P_(j)(m) of the second list to the second CPU₂, where j=1, 2, . . . , m; comparing, by using a comparator of the circuitry, the burst time of the process P_(j)(m) of the second list to the second quantum q₂, if the burst time of the process P_(j)(m) is less than the second quantum, running, by CPU₂, the process P_(j)(m) to generate an output, O_(j); if the burst time of the process P_(j)(m) is greater than the second quantum, running the process P_(j)(m) for a time equal to the second quantum, and adding a remaining burst time of the process P_(j)(m) to a tail of the second list.
 17. The non-transitory computer readable medium method of claim 15, further comprising assigning, by the scheduler, a second process, P_(i+1)(n), to CPU₁; running the second process, P_(i+1)(n), until either the process ends and generates an output O_(i+1) or the quantum q₁ expires; transmitting the output O_(i+1) to an I/O port if the process ends; adding the remainder of the second process, P_(i+1)(n), to the tail of the first list; assigning each next process of the first list to CPU₁, running each next process of the first list, transmitting either the output to an I/O port or adding a remainder of next process to the tail of the first list, until O_(n) outputs are generated.
 18. The non-transitory computer readable medium method of claim 16, further comprising assigning, by the scheduler, a second process, P_(j+1)(m), to CPU₂; running the second process, P_(j+1)(m), until either the process ends and generates an output O_(j+1) or the quantum q₂ expires; transmitting the output O_(j+1) to an I/O port if the process ends; adding the remainder of the second process, P_(j+1)(m), to the tail of the second list; assigning each next process of the second list to CPU₂, running each next process of the second list, and transmitting either the output to an I/O port or adding a remainder of next process to the tail of the second list, until O_(m) outputs are generated.
 19. The non-transitory computer readable medium method of claim 14, further comprising assigning, by the scheduler, a first process P₁(n) of the first list to the first CPU₁; simultaneously assigning, by the scheduler, a first process P₁(m) of the second list to the second CPU₂; comparing, by using a comparator of the circuitry, the burst time of the process P₁(n) to the first quantum q₁, if the burst time of the process P₁(n) is less than the first quantum, running, by CPU₁, the process P₁(n) to generate an output, O₁(n); if the burst time of the process P₁(n) is greater than the first quantum, running the process P₁(n) for a time equal to the first quantum, adding a remaining burst time of the process P₁(n) to a tail of the first list, and assigning a second process P₂(n) from the first list to CPU₁; comparing, by using the comparator, the burst time of the process P₁(m) of the second list to the second quantum q₂; if the burst time of the process P₁(m) is less than the second quantum, running, by CPU₂, the process P₁(m) to generate an output, O_(j)(m); if the burst time of the process P₁(m) is greater than the second quantum, running the process P₁(m) for a time equal to the second quantum, adding a remaining burst time of the process P₁(m) to a tail of the second list, and assigning a second process P₂(m) from the second list to CPU₂.
 20. The non-transitory computer readable medium method of claim 19, further comprising assigning each next process P_(i)(n) of the first list to CPU₁; running each next process P_(i)(n); if P_(i)(n) terminates, transmitting the output O_(i)(n) to an I/O port; if P_(i)(n) does not terminate, adding a remainder of P_(i)(n) to the tail of the first list; continuing to assign and run each next process until O_(n) outputs are generated; assigning each next process P_(j)(m) of the second list to CPU₂; running each next process P_(j)(m); if P_(j)(m) terminates, transmitting the output O_(j)(m) to an I/O port; if P_(j)(m) does not terminate, adding a remainder of P_(j)(m) to the tail of the second list; continuing to assign and run each next process until O_(m) outputs are generated. 